Emulation sits between simulation and experimentation to complete the set of tools available for software designers to evaluate their software and predict behavior under condition...
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
We consider the estimation of the locations of multiple transmitters based on received signal strength measurements at a network of randomly-placed receivers. We generalize the ex...
Jill K. Nelson, Jaime E. Almodovar, Maya R. Gupta,...
—We introduce a 3-dimensional Markov chain that integrates the IEEE 802.11 DCF contention resolution and queueing processes into one model. Important QoS measures, delay and loss...