— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
— This paper presents ATLAS - a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arrang...
—Most publications on the capacity and performance of wireless ad hoc networks share the underlying assumption of a uniform random distribution of nodes. In this paper, we study ...
—Physical Carrier Sensing plays a crucial role in the effectiveness of CSMA-based MAC protocols, yet its properties and impact on the system performance under slow fading channel...
— Delay tolerant networks (DTNs) are a class of networks that experience frequent and long-duration partitions due to sparse distribution of nodes. The topological impairments ex...