974 search results - page 187 / 195 » Simulation blocks for TOSSIM-T2 |
222
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ASPLOS
1992
ACM
15 years 10 months ago
1992
ACM
Given the decreasing cost of non-volatile RAM (NVRAM), by the late 1990's it will be feasible for most workstations to include a megabyte or more of NVRAM, enabling the desig...
155
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ASPLOS
1992
ACM
15 years 10 months ago
1992
ACM
We describe and evaluate a strategy for declustering the parity encoding in a redundant disk array. This declustered parity organization balances cost against data reliability and...
171
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CF
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
213
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DIALM
2007
ACM
15 years 9 months ago
2007
ACM
Sketches--data structures for probabilistic, duplicate insensitive counting--are central building blocks of a number of recently proposed network protocols, for example in the con...
163
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CGO
2004
IEEE
15 years 9 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...