Characterizing shared-memory applications provides insight to design efficient systems, and provides awareness to identify and correct application performance bottlenecks. Configu...
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
In spirit of the earlier works done by Arthur (1992) and Palmer et al. (1993), this paper models speculators with genetic programming (GP) in a production economy (Muthian Economy)...
State of the art, real-time, rate-adaptive, multimedia applications adjust their transmission rate to match the available network capacity. Unfortunately, this source-based rate-a...
We present the Genetic L-System Programming (GLP) paradigm for evolutionary creation and development of parallel rewrite systems (Lsystems, Lindenmayer-systems) which provide a com...