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DATE
2008
IEEE
170views Hardware» more  DATE 2008»
16 years 28 days ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
16 years 27 days ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder
ICCD
2008
IEEE
167views Hardware» more  ICCD 2008»
16 years 27 days ago
Exploiting spare resources of in-order SMT processors executing hard real-time threads
— We developed an SMT processor that allows a static WCET analysis of several hard real-time threads and uses the remaining resources for soft or non real-time threads. The analy...
Jörg Mische, Sascha Uhrig, Florian Kluge, The...
ICDCS
2008
IEEE
16 years 27 days ago
Strong WORM
We introduce a Write-Once Read-Many (WORM) storage system providing strong assurances of data retention and compliant migration, by leveraging trusted secure hardware in close dat...
Radu Sion
IEEEPACT
2008
IEEE
16 years 26 days ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...