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CONPAR
1994
15 years 11 months ago
The Rewrite Rule Machine Node Architecture and Its Performance
The Rewrite Rule Machine (RRM) is a massively parallel MIMD/SIMD computer designed with the explicit purpose of supporting veryhigh-level parallel programming with rewrite rules. T...
Patrick Lincoln, José Meseguer, Livio Ricci...
APCSAC
2004
IEEE
15 years 10 months ago
Continuous Adaptive Object-Code Re-optimization Framework
Dynamic optimization presents opportunities for finding run-time bottlenecks and deploying optimizations in statically compiled programs. In this paper, we discuss our current impl...
Howard Chen, Jiwei Lu, Wei-Chung Hsu, Pen-Chung Ye...
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
15 years 10 months ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
ECRTS
2004
IEEE
15 years 10 months ago
Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations
This paper targets energy-efficient scheduling of tasks over multiple processors, where tasks share a common deadline. Distinct from many research results on heuristics-based ener...
Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, C...
EUC
2006
Springer
15 years 10 months ago
Data-Layout Optimization Using Reuse Distance Distribution
As the ever-increasing gap between the speed of processor and the speed of memory has become the cause of one of primary bottlenecks of computer systems, modern architecture system...
Xiong Fu, Yu Zhang, Yiyun Chen