4747 search results - page 425 / 950 » Shuffle Memory System |
217
Voted
ICDCS
1997
IEEE
15 years 11 months ago
1997
IEEE
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
196
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ITC
1996
IEEE
15 years 11 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
149
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
182
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APCSAC
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
178
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...