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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
HPDC
2000
IEEE
15 years 11 months ago
Failure-Atomic File Access in an Interposed Network Storage System
This paper presents a recovery protocol for block I/O operations in Slice, a storage system architecture for highspeed LANs incorporating network-attached block storage. The goal ...
Darrell C. Anderson, Jeffrey S. Chase
ICCD
2000
IEEE
87views Hardware» more  ICCD 2000»
15 years 11 months ago
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a ...
Subarnarekha Sinha, Sunil P. Khatri, Robert K. Bra...
IPPS
2000
IEEE
15 years 11 months ago
Register Assignment for Software Pipelining with Partitioned Register Banks
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...
ITCC
2000
IEEE
15 years 11 months ago
Towards Knowledge Discovery from WWW Log Data
As the result of interactions between visitors and a web site, an http log file contains very rich knowledge about users on-site behaviors, which, if fully exploited, can better c...
Feng Tao, Fionn Murtagh