Sciweavers

3068 search results - page 218 / 614
» Separation Results on the
Sort
View
ICCAD
2000
IEEE
74views Hardware» more  ICCAD 2000»
15 years 11 months ago
Simultaneous Gate Sizing and Fanout Optimization
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
ASPDAC
2000
ACM
120views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Data memory minimization by sharing large size buffers
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
Hyunok Oh, Soonhoi Ha
ASPDAC
1999
ACM
112views Hardware» more  ASPDAC 1999»
15 years 11 months ago
Relaxed Simulated Tempering for VLSI Floorplan Designs
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new...
Jason Cong, Tianming Kong, Dongmin Xu, Faming Lian...
ISPD
1999
ACM
94views Hardware» more  ISPD 1999»
15 years 11 months ago
Gate sizing with controlled displacement
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
ECRTS
1999
IEEE
15 years 11 months ago
Improved scheduling of control tasks
The paper considers the implementation of digital controllers as real-time tasks in priority-preemptive systems. The performance of a digital feedback control system depends criti...
Anton Cervin