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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
14 years 10 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
EDBT
2011
ACM
222views Database» more  EDBT 2011»
14 years 10 months ago
The hidden web, XML and the Semantic Web: scientific data management perspectives
The World Wide Web no longer consists just of HTML pages. Our work sheds light on a number of trends on the Internet that go beyond simple Web pages. The hidden Web provides a wea...
Fabian M. Suchanek, Aparna S. Varde, Richi Nayak, ...
NAR
2011
208views Computer Vision» more  NAR 2011»
14 years 9 months ago
MIPS: curated databases and comprehensive secondary data resources in 2010
The Munich Information Center for Protein Sequences (MIPS at the Helmholtz Center for Environmental Health, Neuherberg, Germany) has many years of experience in providing annotate...
Hans-Werner Mewes, Andreas Ruepp, Fabian J. Theis,...
COMPSAC
1996
IEEE
15 years 11 months ago
Handling Multimedia Data for Mobile Computers
Mobile clients have unusual needs for sending and receiving multimedia data. The traditional client/server paradigm does not take into account variable network conditions; thus tr...
Charles E. Perkins
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 10 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha