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DAC
2009
ACM
16 years 7 months ago
Generating test programs to cover pipeline interactions
Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, ...
DAC
2002
ACM
16 years 7 months ago
Exploiting shared scratch pad memory space in embedded multiprocessor systems
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhar...
MOBISYS
2007
ACM
16 years 6 months ago
Addressing security in medical sensor networks
We identify the security challenges facing a sensor network for wireless health monitoring, and propose an architecture called "SNAP" (Sensor Network for Assessment of P...
Kriangsiri Malasri, Lan Wang
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
16 years 3 months ago
Routed Inter-ALU Networks for ILP Scalability and Performance
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
Karthikeyan Sankaralingam, Vincent Ajay Singh, Ste...
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
16 years 3 months ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa