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DATE
2003
IEEE
151views Hardware» more  DATE 2003»
16 years 2 days ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
ROBOCUP
1999
Springer
129views Robotics» more  ROBOCUP 1999»
15 years 11 months ago
The Ulm Sparrows 99
In RoboCup-98, sparrows team worked hard just to get both a simulation and a middle size robot team to work and to successfully participate in a major tournament. For this year, we...
Stefan Sablatnög, Stefan Enderle, Mark Dettin...
TCS
2010
15 years 5 months ago
Canonical finite state machines for distributed systems
There has been much interest in testing from finite state machines (FSMs) as a result of their suitability for modelling or specifying state-based systems. Where there are multip...
Robert M. Hierons
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
15 years 11 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
HPCA
1998
IEEE
15 years 11 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...