4312 search results - page 343 / 863 » Semi-User-Level Communication Architecture |
189
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IESS
2007
Springer
16 years 27 days ago
2007
Springer
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
167
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GLOBECOM
2006
IEEE
16 years 25 days ago
2006
IEEE
— Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The SwitchMemory-Switch...
156
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ASPLOS
2006
ACM
16 years 22 days ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
207
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IEEEPACT
2002
IEEE
15 years 11 months ago
2002
IEEE
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
152
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AGENTS
2000
Springer
15 years 11 months ago
2000
Springer
Multi-agent systems are prone to failures typical of any distributed system. Agents and resources may become unavailable due to machine crashes, communication breakdowns, process ...