In this paper, we propose a tactile sensing element that communicates through two dimensional conductive skin layers without individual wires. Each tactile element has sensors and...
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
Abstract—In this paper we focus on optimizing the performance in a cluster of Simultaneous Multithreading (SMT) processors connected with a commodity interconnect (e.g. Gbit Ethe...
Georgios I. Goumas, Nikos Anastopoulos, Nectarios ...