In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...
In this research, an architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed. The proposed architecture reduces the hardware requi...
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
— We propose a new internetworking architecture that represents a departure from current philosophy and practice, as a contribution to the ongoing debate regarding the future Int...
Rudra Dutta, George N. Rouskas, Ilia Baldine, Arno...