4312 search results - page 175 / 863 » Semi-User-Level Communication Architecture |
178
click to vote
HPCA
2000
IEEE
15 years 11 months ago
2000
IEEE
The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophi...
167
click to vote
ISCC
2000
IEEE
15 years 11 months ago
2000
IEEE
Performance modeling and evaluation techniques are essential when designing and implementing distributed software systems. Constructing performance models for such systems can req...
167
click to vote
MOBICOM
2006
ACM
16 years 14 days ago
2006
ACM
In this paper, different deployment strategies for two-dimensional and three-dimensional communication architectures for UnderWater Acoustic Sensor Networks (UW-ASNs) are proposed...
204
click to vote
JSA
2010
15 years 1 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
191
click to vote
CCR
2006
15 years 6 months ago
2006
We describe a system in which layer 2 switching is placed directly under the control of layer 3 routing protocols on a hop-by-hop basis. Specifically, ATM switching is controlled ...