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ETS
2007
IEEE
105views Hardware» more  ETS 2007»
16 years 25 days ago
Communication-Centric SoC Debug Using Transactions
— The growth in System-on-Chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip...
Bart Vermeulen, Kees Goossens, Remco van Steeden, ...
ACSD
2006
IEEE
129views Hardware» more  ACSD 2006»
16 years 17 days ago
Communicating with Synchronized Environments
In the modern design environments, different modules, available in existent libraries, may obey different architectural styles and execution models. Reaching a well– behaved com...
Tiberiu Seceleanu, Axel Jantsch
WADS
2005
Springer
132views Algorithms» more  WADS 2005»
15 years 12 months ago
Communication-Aware Processor Allocation for Supercomputers
Abstract. We give processor-allocation algorithms for grid architectures, where the objective is to select processors from a set of available processors to minimize the average num...
Michael A. Bender, David P. Bunde, Erik D. Demaine...
GI
2004
Springer
15 years 12 months ago
QoS-aware cross-layer communication for Mobile Web services with the WS-QoS framework
: QoS issues will play an important role for the success of Web services. With the increasing number of mobile devices consuming Web services, specific QoS mechanisms are required ...
Min Tian, Andreas Gramm, Hartmut Ritter, Jochen H....
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
15 years 11 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli