Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
In the paper, we describe a series of stages in the development of a new virtual locomotion device designed to enhance remote, interpersonal communications. The latest system, cal...
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
A critical step in all quartet methods for constructing evolutionary trees is the inference of the topology for each set of four sequences (i.e. quartet). It is a well–known fact...
Vincent Berry, Tao Jiang, Paul E. Kearney, Ming Li...
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...