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VTS
2002
IEEE
101views Hardware» more  VTS 2002»
15 years 11 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
VR
2000
IEEE
138views Virtual Reality» more  VR 2000»
15 years 10 months ago
Development of Ground Surface Simulator for Tel-E-Merge System
In the paper, we describe a series of stages in the development of a new virtual locomotion device designed to enhance remote, interpersonal communications. The latest system, cal...
Haruo Noma, Toshiaki Sugihara, Tsutomu Miyasato
DAC
2000
ACM
15 years 10 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
ESA
1999
Springer
82views Algorithms» more  ESA 1999»
15 years 10 months ago
Quartet Cleaning: Improved Algorithms and Simulations
A critical step in all quartet methods for constructing evolutionary trees is the inference of the topology for each set of four sequences (i.e. quartet). It is a well–known fact...
Vincent Berry, Tao Jiang, Paul E. Kearney, Ming Li...
VTS
1999
IEEE
81views Hardware» more  VTS 1999»
15 years 10 months ago
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
Debashis Nayak, D. M. H. Walker