The scheduler is a key component in determining the overall performance of a parallel computer, and as we show here, the schedulers in wide use today exhibit large unexplained gap...
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
— In the context of Independent Component Analysis (ICA), we propose a simple method for online estimation of activation functions in order to blindly separate instantaneous mixt...
As the demands on quality of service (QoS) of real-time applications over the Internet increase, many research efforts have developed various packet scheduling schemes to support ...
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...