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ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 3 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
16 years 3 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
ICCAD
2008
IEEE
161views Hardware» more  ICCAD 2008»
16 years 3 months ago
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu ...
ICCAD
2006
IEEE
130views Hardware» more  ICCAD 2006»
16 years 3 months ago
On bounding the delay of a critical path
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
Leonard Lee, Li-C. Wang
ICCAD
2002
IEEE
73views Hardware» more  ICCAD 2002»
16 years 3 months ago
Shaping interconnect for uniform current density
As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. ...
Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, ...