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DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 11 months ago
Verification of the RF Subsystem within Wireless LAN System Level Simulation
Today’s mobile communication systems use sophisticated signal processing to achieve high transmission rates. Therefore a high complexity in the digital system part as well as ve...
Uwe Knöchel, Thomas Markwirth, Jürgen Ha...
FDL
2003
IEEE
15 years 11 months ago
Synchronization of analogue and digital solvers in mixed-signal simulation on a SystemC platform
This contribution proposes a synchronization technique for solvers able to handle analogue extensions to SystemC, for modelling of general, mixed-mode systems with digital and non...
Tom J. Kazmierski, Hessa Al-Junaid
BMAS
2000
IEEE
15 years 10 months ago
Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS
— Sigma-Delta digital to analog converters are less vulnerable to circuit imperfections than their A/D counterparts because they have their noise-shaping loop all in the digital ...
Martin Vogels, Bart De Smedt, Georges G. E. Gielen
IPPS
1999
IEEE
15 years 10 months ago
Scalable Parallelization of Harmonic Balance Simulation
Abstract. A new approach to parallelizing harmonic balance simulation is presented. The technique leverages circuit substructure to expose potential parallelism in the form of a di...
David L. Rhodes, Apostolos Gerasoulis
ACSD
1998
IEEE
90views Hardware» more  ACSD 1998»
15 years 10 months ago
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
Miroslav N. Velev, Randal E. Bryant