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SAMOS
2010
Springer
15 years 4 months ago
Programming multi-core architectures using Data-Flow techniques
Abstract—In this paper we present a Multithreaded programming methodology for multi-core systems that utilizes DataFlow concurrency. The programmer augments the program with macr...
Samer Arandi, Paraskevas Evripidou
JPDC
2006
85views more  JPDC 2006»
15 years 6 months ago
Provable algorithms for parallel generalized sweep scheduling
We present provably efficient parallel algorithms for sweep scheduling, which is a commonly used technique in Radiation Transport problems, and involves inverting an operator by i...
V. S. Anil Kumar, Madhav V. Marathe, Srinivasan Pa...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 11 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
LCTRTS
2007
Springer
16 years 6 days ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
CASES
2001
ACM
15 years 9 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu