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» Scheduling in the Z-Polyhedral Model
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DAC
1996
ACM
15 years 10 months ago
Issues and Answers in CAD Tool Interoperability
CAD tool interoperability issues are a recurring impediment to constructing a design methodology, especially if the methodology incorporates point tools from several vendors. Failu...
Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trive...
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 10 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
DAC
1992
ACM
15 years 10 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
MICRO
1990
IEEE
147views Hardware» more  MICRO 1990»
15 years 10 months ago
Motivation and framework for using genetic algorithms for microcode compaction
Genetic algorithms are a robust adaptive optimization technique based on a biological paradigm. They perform efficient search on poorly-defined spaces by maintaining an ordered po...
Steven J. Beaty, Darrell Whitley, Gearold Johnson
ICCD
2007
IEEE
150views Hardware» more  ICCD 2007»
15 years 10 months ago
CAP: Criticality analysis for power-efficient speculative multithreading
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
James Tuck, Wei Liu, Josep Torrellas