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ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
16 years 1 days ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
RTAS
2003
IEEE
16 years 23 hour ago
Real-Time Scheduling of Hierarchical Reward-Based Tasks
A reward-based task typically consists of a mandatory part that must be accomplished before the given deadline, and an optional part that is associated with rewards for partial co...
Ming Zu, Albert Mo Kim Cheng
ICPADS
1998
IEEE
15 years 11 months ago
Symbolic Partitioning and Scheduling of Parameterized Task Graphs
The DAG-based task graph model has been found effective in scheduling for performance prediction and optimization of parallel applications. However the scheduling complexity and s...
Michel Cosnard, Emmanuel Jeannot, Tao Yang
DAC
1989
ACM
15 years 10 months ago
Scheduling and Binding Algorithms for High-Level Synthesis
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
Pierre G. Paulin, John P. Knight
CPAIOR
2006
Springer
15 years 10 months ago
Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs
Abstract. In this paper we introduce a complex allocation and scheduling problem for variable voltage Multi-Processor System-on-Chip (MPSoC) platforms. We propose a methodology to ...
Luca Benini, Davide Bertozzi, Alessio Guerri, Mich...