Sciweavers

1758 search results - page 311 / 352
» Schedule processes, not VCPUs
Sort
View
CODES
2003
IEEE
15 years 12 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
ICTAI
2003
IEEE
15 years 12 months ago
An Intelligent Early Warning System for Software Quality Improvement and Project Management
One of the main reasons behind unfruitful software development projects is that it is often too late to correct the problems by the time they are detected. It clearly indicates th...
Xiaoqing Frank Liu, Gautam Kane, Monu Bambroo
ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
15 years 12 months ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti
MM
2003
ACM
161views Multimedia» more  MM 2003»
15 years 12 months ago
MuSA.RT: music on the spiral array. real-time
We present MuSA.RT, Opus 1, a multimodal interactive system for music analysis and visualization using the Spiral Array model. Real-time MIDI input from a live performance is proc...
Elaine Chew, Alexandre R. J. François
AINA
2010
IEEE
15 years 11 months ago
Active Data Selection for Sensor Networks with Faults and Changepoints
Abstract—We describe a Bayesian formalism for the intelligent selection of observations from sensor networks that may intermittently undergo faults or changepoints. Such active d...
Michael A. Osborne, Roman Garnett, Stephen J. Robe...