1758 search results - page 287 / 352 » Schedule processes, not VCPUs |
181
click to vote
RTAS
2008
IEEE
16 years 1 months ago
2008
IEEE
Many wireless sensor nodes (motes) interface with slow peripheral devices, requiring the processor to wait. These delays waste time, energy and power, which are valuable but limit...
187
click to vote
ACISP
2008
Springer
16 years 1 months ago
2008
Springer
Abstract. We present two (related) dedicated hash functions that deliberately borrow heavily from the block ciphers that appeared in the final stages of the AES process. We explor...
152
click to vote
AIMSA
2008
Springer
16 years 1 months ago
2008
Springer
Integrated modeling of temporal and logical constraints is important for solving real-life planning and scheduling problems. Logical constrains extend the temporal formalism by rea...
157
click to vote
FDL
2007
IEEE
16 years 1 months ago
2007
IEEE
This article introduces the Time Model subprofile of MARTE, a new OMG UML Profile dedicated to Modeling and Analysis of Real-Time and Embedded systems. After a brief presentatio...
165
click to vote
NOCS
2007
IEEE
16 years 28 days ago
2007
IEEE
Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs n...