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SAMOS
2004
Springer
15 years 11 months ago
A Novel Data-Path for Accelerating DSP Kernels
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
ESTIMEDIA
2004
Springer
15 years 11 months ago
Data assignment and access scheduling exploration for multi-layer memory architectures
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
ICCAD
1999
IEEE
153views Hardware» more  ICCAD 1999»
15 years 10 months ago
Cycle time and slack optimization for VLSI-chips
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
Christoph Albrecht, Bernhard Korte, Jürgen Sc...
ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
15 years 10 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram