In this paper, a runtime performance projection model for dynamic power management is proposed. The model is built as a first-order linear equation using a linear regression model....
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
— Optimal bandwidth utilisation together with resilience and recovery from failure are two key drivers for Traffic Engineering (TE) which have been widely addressed by the IP co...
We propose an operational method to extract the left ventricle (LV) systole dynamics using HARmonic Phase (HARP) images extracted from tagged cardiac MR sequences. Established tec...
Luc Florack, Hans C. van Assen, Avan Suinesiaputra