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FPL
2010
Springer
124views Hardware» more  FPL 2010»
15 years 4 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
INFOCOM
2012
IEEE
13 years 9 months ago
Fair background data transfers of minimal delay impact
—In this paper we present a methodology for the design of congestion control protocols for background data transfers that have a minimal delay impact on short TCP transfers and c...
Costas Courcoubetis, Antonis Dimakis
ICDCS
2012
IEEE
13 years 9 months ago
Scalable Name Lookup in NDN Using Effective Name Component Encoding
—Name-based route lookup is a key function for Named Data Networking (NDN). The NDN names are hierarchical and have variable and unbounded lengths, which are much longer than IPv...
Yi Wang, Keqiang He, Huichen Dai, Wei Meng, Junche...
BMCBI
2005
108views more  BMCBI 2005»
15 years 6 months ago
A linear memory algorithm for Baum-Welch training
Background: Baum-Welch training is an expectation-maximisation algorithm for training the emission and transition probabilities of hidden Markov models in a fully automated way. I...
István Miklós, Irmtraud M. Meyer
QEST
2005
IEEE
16 years 2 days ago
iLTLChecker: A Probabilistic Model Checker for Multiple DTMCs
iLTL is a probabilistic temporal logic that can specify properties of multiple discrete time Markov chains (DTMCs). In this paper, we describe two related tools: MarkovEstimator a...
YoungMin Kwon, Gul A. Agha