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MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
16 years 1 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
16 years 1 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
SECON
2008
IEEE
16 years 1 months ago
SYNAPSE: A Network Reprogramming Protocol for Wireless Sensor Networks Using Fountain Codes
—Wireless reprogramming is a key functionality in Wireless Sensor Networks (WSNs). In fact, the requirements for the network may change in time, or new parameters might have to b...
Michele Rossi, Giovanni Zanca, Luca Stabellini, Ri...
ISCA
2007
IEEE
161views Hardware» more  ISCA 2007»
16 years 29 days ago
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and...
Christopher J. Hughes, Radek Grzeszczuk, Eftychios...
MSS
2007
IEEE
153views Hardware» more  MSS 2007»
16 years 28 days ago
Hybrid Host/Network Topologies for Massive Storage Clusters
The high demand for large scale storage capacity calls for the availability of massive storage solutions with high performance interconnects. Although cluster file systems are rap...
Asha Andrade, Ungzu Mun, Dong Hwan Chung, Alexande...