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2000
IEEE
128views Hardware» more  DATE 2000»
15 years 11 months ago
A Bus Delay Reduction Technique Considering Crosstalk
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
Kei Hirose, Hiroto Yasuura
PARELEC
2000
IEEE
15 years 11 months ago
Implementation of an Adaptive Reconfigurable Group Organized (ARGO) Parallel Architecture
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
Lucas Szajek, Lev Kirischian
ISLPED
2000
ACM
99views Hardware» more  ISLPED 2000»
15 years 11 months ago
Practical considerations of clock-powered logic
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
William C. Athas
DAC
1999
ACM
15 years 11 months ago
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
IUI
1999
ACM
15 years 11 months ago
Multi-Agent Learning Approach to WWW Information Retrieval Using Neural Network
er has outlined the potential of multiagent framework for decision support. From an abstract point of view, the concept of an agent has been used as modularization principle for th...
Yong S. Choi, Suk I. Yoo