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ASPDAC
2009
ACM
155views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Variation-aware resource sharing and binding in behavioral synthesis
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
Feng Wang 0004, Yuan Xie, Andres Takach
ETFA
2008
IEEE
16 years 1 months ago
Evaluation of Sequential Function Charts execution techniques. The Active Steps Algorithm
Programmable Logic Controllers (PLCs) play a significant role in the control of production systems and Sequential Function Chart (SFC) is one of the main programming languages. Th...
Ramon Piedrafita Moreno, José Luis Villarro...
MICRO
2008
IEEE
153views Hardware» more  MICRO 2008»
16 years 1 months ago
CPR: Composable performance regression for scalable multiprocessor models
Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increas...
Benjamin C. Lee, Jamison D. Collins, Hong Wang 000...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
16 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ICC
2007
IEEE
138views Communications» more  ICC 2007»
16 years 1 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi