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» Scale in Chip Interconnect requires Network Technology
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ESWS
2008
Springer
15 years 7 months ago
xOperator - Interconnecting the Semantic Web and Instant Messaging Networks
Instant Messaging (IM) is in addition to Web and Email the most popular service on the Internet. With xOperator we present a strategy and implementation which deeply integrates Ins...
Sebastian Dietzold, Jörg Unbehauen, Söre...
TCAD
2010
105views more  TCAD 2010»
15 years 21 days ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
ICCAD
2008
IEEE
161views Hardware» more  ICCAD 2008»
16 years 2 months ago
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu ...
CASES
2005
ACM
15 years 8 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
16 years 11 days ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li