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DAC
1995
ACM
15 years 10 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
EURODAC
1995
IEEE
151views VHDL» more  EURODAC 1995»
15 years 10 months ago
Model of conceptual design of complex electronic systems
Due to the ever increasing complexity of electronic system (ES) design, the conceptual design phase and its realization in later phases of the design stream have become increasing...
Alexander N. Soloviev, Alexander L. Stempkovsky
ICCAD
1995
IEEE
114views Hardware» more  ICCAD 1995»
15 years 10 months ago
Sequential synthesis using S1S
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
ISLPED
1995
ACM
85views Hardware» more  ISLPED 1995»
15 years 10 months ago
Estimation of energy consumption in speed-independent control circuits
Abstract: We describe a technique to estimate the energy consumed by speed-independent asynchronous (clockless) control circuits. Because speed-independent circuits are hazard-free...
Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar
ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
15 years 10 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri