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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
16 years 16 days ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
PDIS
1994
IEEE
15 years 10 months ago
Achieving Transaction Scaleup on Unix
Constructing scalable high-performance applications on commodity hardware running the Unix operating system is a problem that must be addressed in several application domains. We ...
Marie-Anne Neimat, Donovan A. Schneider
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 11 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
IEEEPACT
2005
IEEE
15 years 11 months ago
Communication Optimizations for Fine-Grained UPC Applications
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applic...
Wei-Yu Chen, Costin Iancu, Katherine A. Yelick
ACMMSP
2006
ACM
278views Hardware» more  ACMMSP 2006»
16 years 1 days ago
Atomicity via source-to-source translation
We present an implementation and evaluation of atomicity (also known as software transactions) for a dialect of Java. Our implementation is fundamentally different from prior work...
Benjamin Hindman, Dan Grossman