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HIPEAC
2007
Springer
16 years 11 days ago
Performance/Energy Optimization of DSP Transforms on the XScale Processor
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...
Paolo D'Alberto, Markus Püschel, Franz Franch...
CODES
2006
IEEE
16 years 8 days ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu
CODES
2006
IEEE
16 years 8 days ago
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) alo...
Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nali...
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
16 years 6 days ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
ISPASS
2006
IEEE
16 years 6 days ago
Simulation sampling with live-points
Current simulation-sampling techniques construct accurate model state for each measurement by continuously warming large microarchitectural structures (e.g., caches and the branch...
Thomas F. Wenisch, Roland E. Wunderlich, Babak Fal...