2020 search results - page 307 / 404 » Scalable Instruction-Level Parallelism. |
158
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HPDC
2000
IEEE
15 years 10 months ago
2000
IEEE
This paper presents a recovery protocol for block I/O operations in Slice, a storage system architecture for highspeed LANs incorporating network-attached block storage. The goal ...
182
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ICPP
2000
IEEE
15 years 10 months ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
143
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SC
2000
ACM
15 years 10 months ago
2000
ACM
CardioWave is a modular system for simulating wavefront conduction in the heart. These simulations may be used to investigate the factors that generate and sustain life-threatenin...
171
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SPAA
2000
ACM
15 years 10 months ago
2000
ACM
In this paper, we study the design of fault tolerant networks for arrays and meshes by adding redundant nodes and edges. For a target graph G (linear array or mesh in this paper),...
162
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ICDCS
1999
IEEE
15 years 10 months ago
1999
IEEE
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...