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» Scalable Instruction-Level Parallelism.
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SPAA
2010
ACM
15 years 11 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
ICDCS
2000
IEEE
15 years 11 months ago
Highly Concurrent Shared Storage
1 Switched system-area networks enable thousands of storage devices to be shared and directly accessed by end hosts, promising databases and filesystems highly scalable, reliable ...
Khalil Amiri, Garth A. Gibson, Richard A. Golding
ICDCS
2000
IEEE
15 years 11 months ago
Dynamic Adaptive File Management in a Local Area Network
In light of advances in processor and networking technology, especially the emergenceof networkattached disks,the traditional clientserver architecture of file systems has become...
Jiong Yang, Wei Wang 0010, Richard R. Muntz, Silvi...
PDP
2010
IEEE
15 years 11 months ago
Distributed Scheduler of Workflows with Deadlines in a P2P Desktop Grid
Scheduling large amounts of tasks in distributed computing platforms composed of millions of nodes is a challenging goal, even more in a fully decentralized way and with low overhe...
Javier Celaya, Unai Arronategui
ICPADS
1998
IEEE
15 years 10 months ago
Probability Based Replacement Algorithm for WWW Server Arrays
This paper describes a scalable Web server array architecture which uses a caching policy called Probability Based Replacement (PBR) algorithm [5, 6]. The server array consists of...
K. H. Yeung, K. W. Suen