Sciweavers

2020 search results - page 158 / 404
» Scalable Instruction-Level Parallelism.
Sort
View
ICMCS
2006
IEEE
146views Multimedia» more  ICMCS 2006»
16 years 15 days ago
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-He...
ICDM
2005
IEEE
168views Data Mining» more  ICDM 2005»
16 years 2 days ago
A Scalable Collaborative Filtering Framework Based on Co-Clustering
Collaborative filtering-based recommender systems, which automatically predict preferred products of a user using known preferences of other users, have become extremely popular ...
Thomas George, Srujana Merugu
ITCC
2005
IEEE
16 years 1 days ago
A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems
Elliptic Curve Cryptosystems (ECC) have become popular in recent years due to their smaller key sizes than traditional public key schemes such as RSA. However the gap between the ...
Francis M. Crowe, Alan Daly, William P. Marnane
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 11 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
15 years 11 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen