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181
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ISCA
2005
IEEE
16 years 19 hour ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
180
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CLOUD
2010
ACM
15 years 11 months ago
2010
ACM
Failures of any type are common in current datacenters, partly due to the higher scales of the data stored. As data scales up, its availability becomes more complex, while differe...
161
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ICPP
1990
IEEE
15 years 10 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
191
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DEBS
2007
ACM
15 years 10 months ago
2007
ACM
Content-based publish/subscribe systems allow matching the content of events with predicates in the subscriptions. However, most existing systems only allow a limited set of opera...
213
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ISCAPDCS
2004
15 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...