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ATS
2005
IEEE
139views Hardware» more  ATS 2005»
15 years 12 months ago
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
CODES
2005
IEEE
15 years 12 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
15 years 12 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
ICRA
2005
IEEE
124views Robotics» more  ICRA 2005»
15 years 12 months ago
Pattern Generation of Biped Walking Constrained on Parametric Surface
— This paper describes a generation method for spatially natural biped walking. By limiting the COG (Center of Gravity) motion space to a sculptured surface, the degree of freedo...
Mitsuharu Morisawa, Shuuji Kajita, Kenji Kaneko, K...
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
15 years 12 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong