Debugging data races in parallel applications is a difficult task. Error-causing data races may appear to vanish due to changes in an application's optimization level, thread...
Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Peter...
This paper proposes a platform that aims to support the whole process and facilitate archiving tasks at museums and galleries. When we try to preserve tacit knowledge or skills of ...
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
The shared-memory programming model is a very effective way to achieve parallelism on shared memory parallel computers. As great progress was made in hardware and software technolo...
Domain Specific Modeling Languages (DSML) are more and more used to handle high level concepts, and thus bring complex software development under control. The increasingly recurrin...