36 search results - page 3 / 8 » Runtime and quality tradeoffs in FPGA placement and routing |
156
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IFIP
1999
Springer
15 years 10 months ago
1999
Springer
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-...
170
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reco...
152
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FCCM
2006
IEEE
16 years 3 days ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
195
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GLVLSI
2007
IEEE
16 years 12 days ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
168
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DAC
2003
ACM
15 years 11 months ago
2003
ACM
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...