252 search results - page 23 / 51 » Runtime Verification Using a Temporal Description Logic |
183
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SIGSOFT
2007
ACM
16 years 6 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
155
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APLAS
2004
ACM
15 years 9 months ago
2004
ACM
This paper shows how type effect systems can be combined with model-checking techniques to produce powerful, automatically verifiable program logics for higher-order programs. The ...
163
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KBSE
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper describes the application of advanced formal modelling techniques and tools from the CADP toolset to the verification of CFS, a distributed file system kernel. After a ...
140
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CORR
2010
Springer
15 years 6 months ago
2010
Springer
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
151
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VLSID
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...