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ICON
2007
IEEE
16 years 27 days ago
Erlang B as a Performance Model for IP Flows
— Flow-based networking has gained momentum in the research community in recent years. It allows improved performance guarantees and dynamic, load-aware routing. Flowbased networ...
Alexander A. Kist
ISCAS
2007
IEEE
139views Hardware» more  ISCAS 2007»
16 years 26 days ago
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
DEXA
2007
Springer
91views Database» more  DEXA 2007»
16 years 23 days ago
An Evaluation of a Cluster-Based Architecture for Peer-to-Peer Information Retrieval
Abstract. In this paper we provide a full-scale evaluation of a cluster-based architecture for P2P IR, focusing on retrieval effectiveness. We observe that there is a significant ...
Iraklis A. Klampanos, Joemon M. Jose
AHS
2006
IEEE
137views Hardware» more  AHS 2006»
16 years 19 days ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
DSRT
2006
IEEE
16 years 19 days ago
Speedup-Precision Tradeoffs in Time-Parallel Simulation of Wireless Ad hoc Networks
In this paper, we report on a series of experiments involving the speedups obtainable with time-parallel simulation of wireless ad hoc networks. A mobile ad hoc network scenario i...
Damla Turgut, Guoqiang Wang, Ladislau Böl&oum...