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VR
1999
IEEE
154views Virtual Reality» more  VR 1999»
15 years 11 months ago
A Virtual Assembly Design Environment
The Virtual Assembly Design Environment (VADE) is a Virtual Reality (VR) based engineering application which allows engineers to evaluate, analyze, and plan the assembly of mechan...
Sankar Jayaram, Yong Wang, Uma Jayaram, Kevin W. L...
ASE
1998
152views more  ASE 1998»
15 years 6 months ago
Apel: A Graphical Yet Executable Formalism for Process Modeling
Software process improvement requires high level formalisms for describing project-specific, organizational and quality aspects. These formalisms must be convenient not only for ...
Samir Dami, Jacky Estublier, Mahfoud Amiour
HPCA
2003
IEEE
16 years 7 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang
ICSE
2001
IEEE-ACM
15 years 11 months ago
A Scalable Formal Method for Design and Automatic Checking of User Interfaces
The paper addresses the formal specification, design and implementation of the behavioral component of graphical user interfaces. The complex sequences of visual events and action...
Jean Berstel, Stefano Crespi-Reghizzi, Gilles Rous...