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DSD
2009
IEEE
88views Hardware» more  DSD 2009»
15 years 4 months ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
HCI
2007
15 years 8 months ago
Measuring User Experiences of Prototypical Autonomous Products in a Simulated Home Environment
Advances in sensor technology, embedded processing power, and modeling and reasoning software, have created the possibility for everyday products to sense the environment and pro-a...
Martijn H. Vastenburg, David V. Keyson, Huib de Ri...
ICFEM
2010
Springer
15 years 5 months ago
Dynamic Resource Reallocation between Deployment Components
Abstract. Today’s software systems are becoming increasingly configurable and designed for deployment on a plethora of architectures, ranging from sequential machines via multic...
Einar Broch Johnsen, Olaf Owe, Rudolf Schlatte, Si...
CASES
2005
ACM
15 years 8 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...
RTCSA
2009
IEEE
16 years 1 months ago
Branch Target Buffers: WCET Analysis Framework and Timing Predictability
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
Daniel Grund, Jan Reineke, Gernot Gebhard