We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
We present the Genetic L-System Programming (GLP) paradigm for evolutionary creation and development of parallel rewrite systems (Lsystems, Lindenmayer-systems) which provide a com...
Modern network intrusion detection systems need to perform regular expression matching at line rate in order to detect the occurrence of critical patterns in packet payloads. Whil...
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
Biniam Gebremichael, Frits W. Vaandrager, Miaomiao...
After an outline of the history of evolutionary algorithms, a new ( ) variant of the evolution strategies is introduced formally. Though not comprising all degrees of freedom, it i...