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JSA
2010
158views more  JSA 2010»
15 years 1 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
DAC
2002
ACM
16 years 8 months ago
Communication architecture based power management for battery efficient system design
Communication-based power management (CBPM) is a new batterydriven system-level power management methodology in which the systemlevel communication architecture regulates the exec...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
GECCO
2004
Springer
136views Optimization» more  GECCO 2004»
16 years 15 days ago
System Level Hardware-Software Design Exploration with XCS
Abstract. The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip. An Embedded System has to satis...
Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciu...
CODES
2003
IEEE
16 years 12 days ago
Design optimization of mixed time/event-triggered distributed embedded systems
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...
Traian Pop, Petru Eles, Zebo Peng
WSC
1997
15 years 8 months ago
Applications of Discrete Event Simulation in the Design of Automotive Powertrain Manufacturing Systems
Manufacturing automotive powertrain components (engines and transmissions) is a complex task involving the integration of hundreds of components. Simulation is commonly applied in...
Arun Jayaraman, Ali K. Gunal