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VLSID
2007
IEEE
153views VLSI» more  VLSID 2007»
16 years 6 months ago
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
Zhaohui Fu, Sharad Malik
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
16 years 6 months ago
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips
Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices for biochemical analysis. A promising category of microfluidic biochips relie...
Tao Xu, Krishnendu Chakrabarty, Fei Su
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
16 years 6 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
HPCA
2006
IEEE
16 years 6 months ago
Construction and use of linear regression models for processor performance analysis
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
CADE
2007
Springer
16 years 6 months ago
Combination Methods for Satisfiability and Model-Checking of Infinite-State Systems
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...
Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, D...